1. Field of the Invention
Embodiments in accordance with the present disclosure are directed to integrated circuits containing non-volatile memory cell arrays and particularly those arrays incorporating passive element memory cells.
2. Description of the Related Art
Materials having a detectable level of change in state, such as a resistance or phase change, are used to form various types of non-volatile semiconductor based memory devices. For example, simple antifuses are used for binary data storage in one time field-programmable (OTP) memory arrays by assigning a lower resistance initial physical state of a memory cell to a first logical state such as logical ‘0,’ and assigning a higher resistance physical state of the cell to a second logical state such as logical ‘1.’ Some materials can have their resistance switched back in the direction of their initial resistance. These types of materials can be used to form re-writable memory cells. Multiple levels of detectable resistance in materials can further be used to form multi-state devices which may or may not be re-writable.
Materials having a memory effect such as a detectable level of resistance are often used as a state change element and placed in series with a steering element to form a memory cell. Diodes or other devices having a non-linear conduction current are typically used as the steering element. In many implementations, a set of word lines and bit lines are arranged in a substantially perpendicular configuration with a memory cell at the intersection of each word line and bit line. Two-terminal memory cells can be constructed at the intersections with one terminal (e.g., terminal portion of the cell or separate layer of the cell) in contact with the conductor forming the respective word line and another terminal in contactor with the conductor forming the respective bit line. Such cells are sometimes referred to as passive element memory cells.
Two-terminal memory cells with state change elements have been used in three-dimensional field programmable non-volatile memory arrays because of their more simple design when compared to other three-terminal memory devices such as flash EEPROM. Three-dimensional non-volatile memory arrays are attractive because of their potential to greatly increase the number of memory cells that can be fabricated in a given wafer area. In monolithic three-dimensional memories, multiple levels of memory cells can be fabricated above a single substrate, without intervening substrate layers.
One type of three-dimensional memory utilizes a rail-stack structure to form the memory cells. A rail stack is formed by creating successive layers of material which are etched together to form an aligned stack of layers. A memory cell may be formed at the intersection of two such rail stacks. The fabrication of rail-stack structures generally requires fewer mask layers and processing steps to implement an array than other memory structures. The unintentional programming of unselected memory cells is possible in rail-stack structures, particularly with respect to memory cells adjacent to those currently selected. Exemplary memory arrays utilizing rail stacks are described in U.S. Pat. No. 6,631,085 and U.S. Pat. No. 7,022,572.
Another type of three-dimensional memory includes pillars of layers formed at the intersection of upper and lower conductors. Pillar based memory arrays are characterized by the separation of the various structures forming each memory cell from similar structures forming adjacent memory cells. FIGS. 1A-1B are perspective and cross-sectional views, respectively, of a portion of a traditional monolithic three-dimensional memory array. Both the word line and bit line layers are shared between memory cells forming what is often referred to as a fully mirrored structure. A plurality of substantially parallel and coplanar conductors form a first set of bit lines 162 at a first memory level L0. Memory cells 152 at level L0 are formed between these bit lines and adjacent word lines 164. In the arrangement of FIGS. 1A-1B, word lines 164 are shared between memory layers L0 and L1 and thus, further connect to memory cells 170 at memory level L1. A third set of conductors form the bit lines 174 for these cells at level L1. These bit lines 174 are in turn shared between memory levels L1 and memory level L2, depicted in the cross-sectional view of FIG. 1B. Memory cells 178 are connected to bit lines 174 and word lines 176 to form the third memory level L2, memory cells 182 are connected to word lines 176 and bit lines 180 to form the fourth memory level L3, and memory cells 186 are connected to bit lines 180 and word lines 184 to form the fifth memory level L5. Exemplary memory arrays including pillar-based memory cells are described in U.S. Pat. Nos. 5,835,396, 6,034,882 and 6,984,561, each of which is incorporated by reference herein in its entirety.
FIGS. 2A-2F depict a fabrication technique for forming a pillar-type three-dimensional memory array as described in U.S. Pat. No. 6,034,882. A first conductor material 46 and first semiconductor layer stack 45 are deposited as shown in FIG. 2A. The layers are patterned and etched in a first direction to form substantially parallel first conductors 46a and 46b and first etched lines of the semiconductor layer stack in a single masking step as shown in FIG. 2B. The semiconductor layer stack is etched into lines 45a and 45b, but is not yet etched into pillars. The gaps between the lines of semiconductor layer stack and the conductors are filled with dielectric material (not shown) to insulate the wiring and devices from one another.
A second conductor material 50 and second semiconductor layer stack 51 are deposited as shown in FIG. 2C. A second pattern is applied followed by etching in a second direction to form substantially parallel second conductors 50a and 50b and second semiconductor layer stack lines 51a and 51b. The second direction is substantially orthogonal to the first direction. The second etch continues through the second conductors and the first semiconductor layer stack lines, to forming pillars 45a1, 45a2, 45b1 and 45b2. Because they were formed in a shared masking step, two opposing sidewalls of each of the first pillars (e.g. 45a1) are self-aligned with the edges of the first conductor below (e.g. 46a), while the other two opposing sidewalls of each of the first pillars are self-aligned with the edges of the second conductor above (e.g. 50a.) The gaps in between the second conductors and second lines of semiconductor material are filled with dielectric material.
After filling the gaps between adjacent lines, a third conductor material 52 and third semiconductor layer stack 53 are deposited as shown in FIG. 2E. A third pattern is applied, followed by etching again in the first direction as shown in FIG. 2F. The third etch forms substantially parallel third conductors 52a, 52b and third semiconductor layer stack lines 53a, 53b that are substantially perpendicular to the second conductors. The third etch continues through the third conductors and layer stack lines 51a, 51b, forming pillars 51a1, 51a2, 51b1, 51b2. Because they were formed in a shared masking step, the second pillars each have two opposing sidewalls that are self-aligned with the edges of the third conductor (e.g., 52a) above. The other two opposing sidewalls of the second pillars are self-aligned with the edges of the second conductors (e.g., 50a) below as a result of being formed in the shared second masking step.
As FIGS. 2A-2F illustrate, the formation of pillar structures requires precise alignment in forming the small feature sizes of the structures. Numerous processing difficulties may exist in the formation of these structures. For example, the technique in FIGS. 2A-2F etches one conductor layer and two semiconductor layer stacks in each of the masking operations. This technique is effective to self-align the pillars with both the overlying and underlying conductors. However, etching through a significant number of layers in a single etch process can pose its own set of difficulties. The structures may lack stability during various stages of the process. Moreover, the precision necessary in forming the features may be affected by such deep etches. Accordingly, there remains a need for improved three-dimensional pillar designs and corresponding fabrication processes for forming the same in non-volatile memory array technologies.